The present invention relates generally to the manufacture of semiconductor devices, and more particularly to methods of manufacturing semiconductor devices that can limit etch damage and/or provide improved lithography focus margin.
In many semiconductor devices, a substrate may include different regions having different tolerances to certain process steps. As but one example, a semiconductor memory device, such as dynamic random access memory (DRAM), may include a memory cell region that can be separate from peripheral regions. During manufacturing, a memory cell region may experience damage from etching. Etching damage may cause deterioration of circuit characteristics in a memory cell region. As but one example, DRAM memory cell device hold characteristics can deteriorate from etching damage. Device hold characteristics can indicate how long a memory cell can retain a particular logic value.
Various conventional approaches have been proposed to address etching damage to selected portions of a semiconductor device while maintaining a stable and high-throughput process. A first example of art related to such manufacturing processes will now be described with reference to FIGS. 5 to 7. FIGS. 5 to 7 show side cross sectional view of a manufacturing process for a semiconductor memory device having a peripheral circuit region (PERIPHERAL CIRCUIT REGION) and a memory cell region (MEMORY CELL REGION).
Referring now to FIG. 5, a conventional semiconductor manufacturing process may include forming a field oxidation film 002 in a p-type silicon substrate 001. A field oxidation film 002 may separate active region in a p-type substrate 001 from one another. A gate oxidation film (not shown) may also be formed over a substrate 001. A word line 003 comprising polycrystalline silicon may then be formed on a gate oxidation film.
Referring again to FIG. 5, an n-type diffusion layer 004 can then be formed in the substrate 001 on the sides of a word line 003. Such an n-type diffusion layer 004 may include lightly doped diffusion (LDD) regions.
Referring now to FIG. 6, an oxide layer 005 may be deposited over a semiconductor substrate 001, including over diffusion layer 004 and word line 003. An oxide layer 005 can be used to form a sidewall in a peripheral circuit region, and protect a substrate in memory cell region from etch damage. An oxide layer 005 may be formed from well-known techniques, such as high temperature oxide (HTO), and the decomposition of tetraethylorthosilicate (TEOS) to form non-doped silicate glass (NSG), etc. Further, an oxide layer 005 may be deposited to a thickness of approximately 1500 to 2000 angstroms.
FIG. 6 also shows the formation of an etch mask from photoresist 006. A photoresist etch mask 006 may cover a memory cell region and expose a peripheral circuit region.
Referring to FIG. 7, a semiconductor substrate may then be etched with dry etching (anisotropic etching). Such etching can form sidewalls 005-b in a peripheral circuit region. However, due to a photoresist etch mask 006, sidewalls are not formed in a memory cell region.
FIG. 7 also shows the formation of an n-channel and/or p-channel diffusion layers 007. N-channel and/or p-channel diffusion layers 007 may be formed sequentially with photolithographic techniques and ion implantation. Ion implantation may include the implantation of n-type and p-type dopants, for example, arsenic and difluoroborane (BF2), etc. In this way, transistors may be formed in a semiconductor device.
A drawback to various conventional approaches can be added complexity due to narrow focus margins involved in small geometry photolithographic steps. More particularly, if reference is made back to FIG. 7, following the formation of sidewalls 005-b in a peripheral circuit region, an oxide layer 005-a may be formed over a memory cell region. An oxide layer 005-a may have a step height, shown as xe2x80x9cB,xe2x80x9d that is essentially the thickness of a sidewall 005-b. Thus, an oxide layer 005-b may result in a difference in height between a peripheral circuit region and a memory cell region. Such a height difference can reduce focus margins for subsequent photolithography and etch steps. Consequently, to increase focus margins, a conventional approach may include subsequent deposition steps accompanied by chemical-mechanical polishing (CMP). While CMP steps can provide a more level surface, such steps can undesirably increase the number of steps in an overall manufacturing process.
Another example of related art is described in Japanese Laid Open Patent Application (Kokai) 03-062573 titled MIS SEMICONDUCTOR DEVICE MANUFACTURING METHOD. In Kokai 03-062573, n-type diffusion regions and gates may be formed on a substrate. A layer of spin-on-glass (SOG) and a sidewall silicon dioxide film may then be deposited. It is noted that in Kokai 03-062573, a semiconductor device includes a dense metallization region (which can correspond to a memory cell region) and a sparse metallization region (which can correspond to a peripheral region). SOG in combination with a sidewall silicon dioxide film may result in an overall silicon dioxide/SOG film thickness that is the same in both the dense and sparse metallization region. This can reduce etch damage as theoretically, the substrate can be exposed as essentially the same time in both the sparse metallization region and the dense metallization region.
Kokai 03-062573 goes on to describe forming n-channel and p-channel transistors in a self-aligned fashion with photolithographic and ion implantation steps.
Kokai 03-062573 thus illustrates reduction in etch damage to a substrate resulting from a sidewall etch step by forming a sidewall layer with uniform thickness in all regions of a semiconductor device.
A drawback to the second example of Kokai 03-062573 can be that in many cases, despite essentially uniform sidewall layer coverage, etching damage may still occur. Etching damage may occur because actual etch rates may vary over a wafer surface. Further, such variations in etch rates can be greater for larger wafers, which can be preferable for economic reasons.
A third example of related art is described in Japanese Laid Open Patent Application 62-069560 titled MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES. In Kokai 62-069560, gates may be formed on a semiconductor substrate that may then be oxidized to form an oxidation layer. An N-diffusion region can then be formed by ion implantation. A silicon nitride film may then be formed over the surface of a semiconductor substrate. A silicon dioxide film may be formed over the silicon nitride film. When the silicon dioxide film is etched to form sidewall, the silicon nitride film can protect the substrate from etch damage.
Kokai 62-069560 thus illustrates reduction in etch damage to a substrate resulting from a sidewall etch step by forming a silicon nitride layer below a sidewall layer. A similar example of related art is shown in Japanese Laid Open Patent Application 8-330331.
One drawback to the approach of Kokai 62-069560 can be the resulting transistor properties. More particularly, in many cases it can be desirable to perform a hydrogen anneal that can reduce charge trap potential at a semiconductor surface. By forming an initial silicon dioxide layer over the surface, the effects of such a hydrogen anneal are reduced. A second drawback can be increased leakage of such a structure. A silicon nitride film may increase mechanical stress, resulting in greater leakage.
A fourth example of related art is described in Japanese Laid Open Patent Application 3-145136 titled MOS SEMICONDUCTOR DEVICE AND SIDEWALL FORMING METHOD THEREOF. In Kokai 3-145136, a sidewall layer may be a layered structure of different substances. The different substances can have an etch rate differential with respect to one another. Thus, when the sidewall layer is etched to form sidewalls, such an etch differential can result in a material protecting a substrate from etch damage.
It is noted that the fourth example results in a sidewall structure formed from two different materials.
A fifth example of related art is described in Japanese Patent No. 2670265 titled MANUFACTURING METHOD FOR CMOS SEMICONDUCTOR DEVICES. Japanese Patent No. 2670265 shows a semiconductor device having a complementary metal oxide semiconductor (CMOS) arrangement. In a sidewall forming etch step, a p-channel transistor diffusion layer can be prevented from being overetched, which can increase resistance. An object of Japanese Patent No. 2670265 is to prevent a decrease in the electrical current drive capability of transistors.
The fifth example appears to have a different object than the present invention in that an insulating film protects transistors in a peripheral p-channel region from overetch. This is different than the problem addressed by the present invention, which seeks to protect a memory cell region from damage when a peripheral region is etched. Such memory cell regions typically include n-channel transistors.
In light of the above discussion, it would be desirable to arrive at a semiconductor device manufacturing method that can protect a higher density region (e.g., memory cell region) from overetch when sidewalls are formed in a lower density region (e.g., peripheral region). At the same time, such a method should provide for increased focus margins for photolithographic steps, or the like.
According to the present invention, a method of manufacturing a semiconductor apparatus may include forming an isolation region in a semiconductor substrate and forming a gate over a first region. A protective film may then be formed over the first region and a second region. The protective film over the second region may then be removed by isotropic etching. A sidewall layer may be formed over the first and second regions, and then etched to form sidewalls. The protective film over the first region can protect the first region from etch damage. Further, because a protective film may be thinner than a sidewall layer, a step height between a first region and a second region can be reduced. This can result in greater focus margins than conventional approaches and related art.
According to one aspect of the invention, a protective film may have a thickness in the range of 400 to 500 angstroms.
According to another aspect of the invention, a protective film and sidewall layer may be formed separately.
According to another aspect of the invention, focus margins for lithography steps following the formation of gate sidewalls may be improved without chemical-mechanical polishing.